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Preliminary W49V002A 256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACE
GENERAL DESCRIPTION The W49V002A is a 2 -megabit, 3.3-volt only CMOS flash memory organized as 256K x 8 bits. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49V002A results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode and LPC bus interface mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the LPC interface mode, this device complies with the Intel LPC specification 1.0. The device can also be programmed and erased using standard EPROM programmers.
FEATURES
*Single 3.3-volt operations:
bytes, 64K bytes, 64K bytes each)
* Low power consumption
- 3.3-volt Read - 3.3-volt Erase - 3.3-volt Program
* Fast Program operation:
- Active current: 25 mA (typ.) - Standby current: 20 A (typ.)
* Automatic program and erase timing with
- Byte-by-Byte programming: 50 S (typ.)
* Fast Erase operation: 150 mS (typ.) * Endurance: 10K cycles (typ.) * Twenty-year data retention * Hardware data protection
internal VPP generation
* End of program or erase detection
- Toggle bit - Data polling
* Latched address and data * TTL compatible I/O * Available packages: 32L PLCC and 32L
- #TBL & #WP serve as hardware protection
* One 16K bytes Boot Block with lockout
protection
* Two 8K bytes Parameter Blocks * Four Main Memory Blocks (with 32K bytes, 64K
STSOP
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Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
PIN CONFIGURATIONS
A 8 ^ G P I 2 v 4 A7(GPI1) A6(GPI0) A5(#WP) A4(#TBL) A3(RSV) A2(RSV) A1(RSV) A0(RSV) DQ0(LAD0) 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A 9 ^# GR PE IS V 3END vTCD 3 2 R # C ^ C L K v A 1 0 ^ G P I 4 v
PIN DESCRIPTION
SYMB
MODE
29 28 27 MODE GND NC NC VDD #OE(#INIT) #WE(#LFRAM) NC DQ7(RSV)
INTERFACE PGM *
*
PIN NAME
Interface Mode Selection Reset Initialize Top Boot Block Lock Write Protect CLK Input General Purpose Inputs Address/Data Inputs LPC Cycle Initial Row/Column Select Address Inputs Data Inputs/Outputs Output Enable Write Enable
LPC *
* *
1 32 31 30
#RESET #INIT #TBL #WP CLK GPI[4:0] LAD[3:0]
32 31 30 29 28 27 26 #OE(#INIT) #WE(#LFRAM) NC DQ7(RSV) DQ6(RSV) DQ5(RSV) DQ4(RSV) DQ3(LAD3) GND DQ2(LAD2) DQ1(LAD1) DQ0(LAD0) A0(RSV) A1(RSV) A2(RSV) A3(RSV)
32-pin PLCC
26 25 24 23 22 21
* * * * * * * * * * * * * * * * * * *
DDG QQN 12D ^^ LL AA DD 12 vv NC NC NC GND MODE A10(GPI4) R/#C(CLK) VDD NC #RESET A9(GPI3) A8(GPI2) A7(GPI1) A6(GPI0) A5(#WP) A4(#TBL) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DDD QQQ 345 ^^^ L RR ASS DVV 3vv v
D Q 6 ^ R S V v
#LFRAM R/#C A[10:0] DQ[7:0] #OE #WE VDD GND
32-pin TSOP
25 24 23 22 21 20 19 18 17
Power Supply Ground Reserve Pins No Connection
BLOCK DIAGRAM
#WP #TBL CLK LAD[3:0] #LFRAM MODE #INIT #RESET MAIN MEMORY BLOCK1 32K BYTES R/#C A[10:0] DQ[7:0] #OE #WE Programmer Interface MAIN MEMORY BLOCK2 64K BYTES MAIN MEMORY BLOCK3 64K BYTES MAIN MEMORY BLOCK4 64K BYTES LPC Interface BOOT BLOCK 16K BYTES PARAMETER BLOCK1 8K BYTES PARAMETER BLOCK2 8K BYTES 3FFFF 3C000 3BFFF 3A000 39FFF 38000 37FFF 30000 2FFFF
RSV NC
20000 1FFFF
10000 0FFFF 00000
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Preliminary W49V002A
FUNCTIONAL DESCRIPTION
Interface Mode Selection And Description
This device can be operated in two interface modes, one is Programmer interface mode, the other is LPC interface mode. The MODE pin of the device provides the control between these two interface modes. These interface modes need to be configured before power up or return from #RESET. When MODE pin is set to high state, the device is in the Programmer mode; while the MODE pin is set to low state(or leaved no connection), it is in the LPC mode. In Programmer mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed, which go through the address inputs A[10:0]. For LPC mode, It complies with the LPC Interface Specification Revision 1.0. Through LAD[3:0] to communicate with the system chipset .
Read(Write) Mode
In Programmer interface mode, the read(write) operation of the W49V002A is controlled by #OE (#WE). The #OE (#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when #OE is high. As in the LPC interface mode, the read or write is determined by the "bit 1 of CYCLE TYPER+DIR".
Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals.
Chip Erase Operation
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed within fast 100 mS (typical). The host system is not required to provide any control or timing during this operation. If the boot block programming lockout is activated, only the data in the other memory blocks will be erased to FF(hex) while the data in the boot block will not be erased (remains as the same state before the chip erase operation). The entire memory array will be erased to FF(hex) by the chip erase operation if the boot block programming lockout feature is not activated. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
Sector Erase Operation
The seven sectors, one boot block and two parameter blocks and four main blocks, can be erased individually by initiating a six-byte command sequence. Sector address is latched on the falling #WE edge of the sixth cycle, while the 30(hex) data input command is latched at the rising edge of #WE. After the command loading cycle, the device enters the internal sector erase mode, which is automatically timed and will be completed within fast 150 mS (typical). The host system is not required to provide any control or timing during this operation. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
Program Operation
The W49V002A is programmed on a byte-by-byte basis. Program operation can only change logical data Publication Release Date: April 2001 Revision A1
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Preliminary W49V002A
"1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming. The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byte-program command is entered. The internal program timer will automatically time-out (100 S max. - TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle.
Boot Block Operation and Hardware Protection at Initial- #TBL & #WP
There are two alternatives to set the boot block. One is software command sequences method; the other is hardware method. 16K-byte in the top location of this device can be locked as boot block, which can be used to store boot codes. It is located in the last 16K bytes of the memory with the address range from 3C000(hex) to 3FFFF(hex). Please see Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set, the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method. Besides the software method, there is a hardware method to protect the top boot block and other sectors. Before program/erase to this device, set the #TBL pin to low state and then the top boot block will not be programmed/erased. When enabling hardware top boot block, #TBL being low state, it will override the software method setting. That is, if #TBL is at low state, then top boot block cannot be programmed/erased no matter how the software boot block lock setting. Another pin, #WP, will protect the whole chip if this pin is set to low state before program/erase. The enable of this pin will override the #TBL setting. That is, the top boot block cannot be programmed/erased if this pin is set to low no matter how the #TBL or software boot block lock setting.
Hardware Data Protection
The integrity of the data stored in the W49V002A is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 1.5V typical. (3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W49V002A includes a data polling feature to indicate the end of a program or erase cycle. When the W49V002A is in the internal program or erase cycle, any attempts to read DQ7 of the last byte loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and when erase cycle has been completed it becomes logical "1" or true data.
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W49V002A provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. -4 -
Preliminary W49V002A
Memory Address Map
There are 8M bytes space reserved for BIOS Addressing. The ROM will respond to 256K byte pages whenever the memory address rang is within the top 4M bytes and bottom 128K bytes. The 32bit address space is as below: Block 4M Byte BIOS ROM 128K Byte BIOS ROM Registers Address Range FFFF,FFFFh:FFC0,0000h 000F,FFFFh:000E,0000h FFBC,0100h
General Purpose Inputs Register
This register reads the GPI[4:0] pins on the W49V002A.This is a pass-through register which can read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value. Bit 7-5 4 3 2 1 0 Function Reserved Read GPI4 pin status Read GPI3 pin status Read GPI2 pin status Read GPI1 pin status Read GPI0 pin status
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software operation. In the software access mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access the product ID. A read from address 0000(hex) outputs the manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, B0(hex)." The product ID operation can be terminated by a three-byte command sequence or an alternate one-byte command sequence (see Command Definition table).
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Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
TABLE OF OPERATING MODES
Operating Mode Selection - Programmer Mode
(VHH = 12V 5%)
MODE Read Write Standby Write Inhibit Output Disable #OE VIL VIH X VIL X VIH #WE VIH VIL X X VIH X #RESET VIH VIH VIL VIH VIH VIH AIN AIN X X X X
PINS ADDRESS
DQ. Dout Din High Z High Z/DOUT High Z/DOUT High Z
Operating Mode Selection - LPC Mode
Operation modes in LPC interface mode are determined by "cycle type" when it is selected. When it is not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "Standard LPC Memory Cycle Definition". TABLE OF COMMAND DEFINITION
COMMAND DESCRIPTION Read Chip Erase Sector Erase Byte Program Boot Block Lockout Product ID Entry Product ID Exit (1) Product ID Exit
(1)
NO. OF Cycles 1 6 6 4 6 3 3 1
1ST CYCLE Addr. Data A IN DOUT 5555 AA 5555 AA 5555 AA 5555 AA 5555 AA 5555 AA XXXX F0
2ND CYCLE Addr. Data 2AAA 55 2AAA 55 2AAA 55 2AAA 55 2AAA 55 2AAA 55
3RD CYCLE Addr. Data 5555 80 5555 80 5555 A0 5555 80 5555 90 5555 F0
4TH CYCLE Addr. Data 5555 AA 5555 AA A IN DIN 5555 AA
5TH CYCLE Addr. Data 2AAA 55 2AAA 55 2AAA 55
6TH CYCLE Addr. Data 5555 10 SA 30
5555 40
Note: 1. The cycle means the write command cycle not the LPC clock cycle. 2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11] 3. Address Format: A14-A0 (Hex); Data Format: DQ7-DQ0 (Hex) 4. Either one of the two Product ID Exit commands can be used. 5. SA : Sector Address SA = 3C000h to 3FFFFh for Boot Block SA = 3A000h to 3BFFFh for Parameter Block1 SA = 38000h to 39FFFh for Parameter Block2 SA = 30000h to 37FFFh for Main Memory Block1 SA = 2XXXXh for Main Memory Block2 SA = 1XXXXh for Main Memory Block3 SA = 0XXXXh for Main Memory Block4
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Preliminary W49V002A
STANDARD LPC MEMORY CYCLE DEFINITION
FIELD Start Cycle Type & Dir TAR Addr. NO. OF CLOCKS 1 1 2 8 DESCRIPTION "0000b" appears on LPC bus to indicate the initial "010Xb" indicates memory read cycle; while "011xb" indicates memory write cycle. "X" mean don't have to care. Turned Around Time Address Phase for Memory Cycle. LPC supports the 32 bits address protocol. The addresses transfer most significant nibble first and least significant nibble last. (i.e. Address[31:28] on LAD[3:0] first , and Address[3:0] on LAD[3:0] last.) Synchronous to add wait state. "0000b" means Ready, "0101b" means Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error, and other values are reserved. Data Phase for Memory Cycle. The data transfer least significant nibble first and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0] first , then DQ[7:4] on LAD[3:0] last.)
Sync.
N
Data
2
Note: 1. For detail related LPC specification, please refer to Intel LPC spec. 1.0 or later.
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Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
Command Codes for Byte Program
BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write ADDRESS 5555H 2AAAH 5555H Programmed-Address DATA AAH 55H A0H Programmed-Data
Byte Program Flow Chart
Byte Program Command Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555
Load data Din to programmedaddress
Pause TBP
Exit
Notes for software program code: Data Format: DQ7-DQ0 (Hex); XX = Don't Care Address Format: A14-A0 (Hex)
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Preliminary W49V002A
Command Codes for Chip Erase
BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 10H
Chip Erase Acquisition Flow
Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555
Pause T EC
Exit
Notes for chip erase: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex)
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Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
Command Codes for Sector Erase
BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH SA* DATA AAH 55H 80H AAH 55H 30H
Sector Erase Acquisition Flow
Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 30 to address SA*
Pause T EC
Exit Notes for chip erase: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex) SA : Sector Address SA = 3C000h to 3FFFFh for Boot Block SA = 3A000h to 3BFFFh for Parameter Block1 SA = 38000h to 39FFFh for Parameter Block2
SA = 2XXXXh for Main Memory Block2 SA = 1XXXXh for Main Memory Block3
SA = 30000h to 37FFFh for Main Memory Block1 SA = 0XXXXh for Main Memory Block4
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Preliminary W49V002A
Command Codes for Product Identification and Boot Block Lockout Detection
BYTE SEQUENCE SOFTWARE PRODUCT IDENTIFICATION / BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS 1 Write 2 Write 3 Write 5555 2AAA 5555 Pause 10S DATA AA 55 90 SOFTWARE PRODUCT IDENTIFICATION / BOOT BLOCK LOCKOUT DETECTION EXIT (6) ADDRESS 5555H 2AAAH 5555H Pause 10S DATA AAH 55H F0H
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product Identification Entry (1)
Load data AA to address 5555
Product
Identification and Boot Block Lockout Detection Mode (3)
Product Identification Exit(6)
Load data AA to address 5555 (2)
Load data 55 to address 2AAA
Read address = 00000 data = DA
Load data 55 to address 2AAA
Load data 90 to address 5555
Read address = 00001 data = B0
(2)
Load data F0 to address 5555
Pause 10 S
Read address = 00002 DQ0 of data outputs = 1/0
(4)
Pause 10 S
(5) Normal Mode
Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7-DQ0 (Hex); Address Format: A14-A0 (Hex) (2) A1-A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the DQ0 of output data "0," the lockout feature is inactivated and the block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.
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Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
Command Codes for Boot Block Lockout Enable
BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write BOOT BLOCK LOCKOUT FEATURE SET ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H Pause 1 Sec. DATA AAH 55H 80H AAH 55H 40H
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout Feature Set Flow
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 80 to address 5555
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 40 to address 5555
Pause T BP
Exit
Notes for boot block lockout enable: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex)
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Preliminary W49V002A
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential Transient Voltage (<20 nS ) on Any Pin to Ground Potential RATING -0.5 to +4.1 0 to +70 -65 to +150 -0.5 to VDD +0.5 -1.0 to VDD +0.5 UNIT V C C V V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
Programmer interface Mode DC Operating Characteristics
(VDD 3.3V 5%, VGND= 0V, TA = 0 to 70 C)
PARAMETER
SYM.
TEST CONDITIONS
LIMITS MIN. TYP. MAX. 30
UNIT
Power Supply Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
ICC
In Read or Write mode, all DQs open Address inputs = 3.0V/0V, at f = 3 MHz
-
20
mA A A V V V V
ILI ILO VIL VIH VOL VOH
VIN = GND to VDD VOUT = GND to VDD IOL = 2.1 mA IOH = -0.1mA
-0.3 2.0 2.4
-
10 10 0.8 VDD +0.5 0.45 -
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Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
LPC interface Mode DC Operating Characteristics
(VDD = 3.3V 5%, VGND= 0V, TA = 0 to 70 C)
PARAMETER
SYM.
TEST CONDITIONS
LIMITS MIN. TYP. MAX. 60
UNIT
Power Supply Current CMOS Standby Current TTL Standby Current
ICC
All Iout = 0A, CLK = 33MHz, in LPC mode operation.
-
40
mA
Isb1
#LFRAM = 0.9 VDD, CLK = 33MHz, all inputs = 0.9 VDD / 0.1 VDD
-
20
100
uA
Isb2
#LFRAM = 0.1 VDD, CLK = 33MHz, all inputs = 0.9 VDD / 0.1 VDD
-
3
10
mA
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
VIL VIH VOL VOH IOL = 1.5 mA IOH = -0.5 mA
-
-0.3 0.6 VDD 0.9 VDD
-
0.2 VDD VDD +0.5 0.1 VDD -
V V V V
Power-up Timing
PARAMETER Power-up to Read Operation Power-up to Write Operation CAPACITANCE
(VDD = 3.3V, TA = 25 C, f = 1 MHz)
SYMBOL TPU. READ TPU. WRITE
TYPICAL 100 5
UNIT S mS
PARAMETER I/O Pin Capacitance Input Capacitance
SYMBOL CI/O CIN
CONDITIONS VI/O = 0V VIN = 0V
MAX. 12 6
UNIT pf pf
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Preliminary W49V002A
PROGRAMMER INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 0.9VDD < 5 nS 1.5V/1.5V 1 TTL Gate and CL = 30 pF CONDITIONS
AC Test Load and Waveform
+3.3V
1.8K
DOUT
Input
30 pF (Including Jig and Scope) 0.9V DD 1.3K 0V Test Point 1.5V
Output
1.5V
Test Point
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Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
Programmer Interface Mode AC Characteristics, continued
AC Characteristics Read Cycle Timing Parameters
(VDD = 3.3V 5%, VGND = 0V, TA = 0 to 70 C)
PARAMETER Read Cycle Time Row / Column Address Set Up Time Row / Column Address Hold Time Address Access Time Output Enable Access Time #OE Low to Active Output #OE High to High-Z Output Output Hold from Address Change
SYM. TRC TAS TAH TAA TOE TOLZ TOHZ TOH
W49V002A MIN. MAX. 300 50 50 200 100 0 50 0 -
UNIT nS nS nS nS nS nS nS nS
Write Cycle Timing Parameters
PARAMETER Reset Time Address Setup Time Address Hold Time R/#C to Write Enable High Time #WE Pulse Width #WE High Width Data Setup Time Data Hold Time #OE Hold Time Byte programming Time Erase Cycle Time SYMBOL TRST TAS TAH TCWH TWP TWPH TDS TDH TOEH TBP TEC MIN. 1 50 50 50 100 100 50 50 0 TYP. 50 0.15 MAX. 100 0.2 UNIT S nS nS nS nS nS nS nS nS S S
Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is input high and (b) low level signal's reference level is input low. Ref. to the AC testing condition.
Data Polling and Toggle Bit Timing Parameters
PARAMETER #OE to Data Polling Output Delay #OE to Toggle Bit Output Delay SYM. TOEP TOET W49V002A MIN. MAX. 40 40 UNIT nS nS
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Preliminary W49V002A
TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE
Read Cycle Timing Diagram
#RESET TRST TRC Column Address TAS R/#C TAH Row Address TAS TAH Column Address Row Address
A[10:0]
#WE #OE
VIH TAA TOH
T OE High-Z DQ[7:0] TOLZ
T OHZ High-Z Data Valid
Write Cycle Timing Diagram
TRST #RESET
A[10:0]
Column Address TAS TAH
Row Address TAS TAH
R/ #C TCWH #OE TWP #WE TDS DQ[7:0] Data Valid TDH TWPH TOEH
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Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
Timing Waveforms for Programmer Interface Mode, continued
Program Cycle Timing Diagram
Byte Program Cycle A[10:0] (Internal A[17:0]) DQ[7:0] 5555 AA 2AAA 55 5555 A0
Programmed Address
Data-In
R/#C
#OE TWP #WE Byte 0
TWPH
TBP
Byte 1
Byte 2
Byte 3
Internal Write Start
Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11].
#DATA Polling Timing Diagram
A[10:0] (Internal A[17:0]) R/ #C An An An An
#WE
#OE TOEP DQ7 X X X TBP orTEC X
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Preliminary W49V002A
Timing Waveforms for Programmer Interface Mode, continued
Toggle Bit Timing Diagram
A[10:0]
R/ #C
#WE
#OE TOET DQ6 T BP or T EC
Boot Block Lockout Enable Timing Diagram
Six-byte code for 3.3V-only software chip erase A[10:0] (Internal A[17:0]) DQ[7:0] 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
R/#C
#OE #WE
TWP TWPH SB0 SB1 SB2 SB3 SB4 SB5
TWC
Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11].
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Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
Timing Waveforms for Programmer Interface Mode, continued
Chip Erase Timing Diagram
Six-byte code for 3.3V-only software chip erase A[10:0] (Internal A[17:0]) 5555 2AAA 5555 5555 2AAA 5555
DQ[7:0]
AA
55
80
AA
55
10
R/#C
#OE TWP #WE SB0 TWPH SB1 SB2 SB3 SB4 SB5 Internal Erasure Starts TEC
Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11].
Sector Erase Timing Diagram
Six-byte code for 5V-only software Main Memory Erase A[10:0] (Internal A[17:0]) DQ[7:0] 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA 30
R/ #C
#OE #WE
TWP TWPH SB0 SB1 SB2 SB3 SB4 SB5
TEC
Internal Erase starts
Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]. SA = Sector Address, Please ref. to the "Table of Command Definition"
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Preliminary W49V002A
LPC INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise/Fall Slew Rate Input/Output Timing Level Output Load 0.6 VDD to 0.2 VDD 1 V/nS 0.4VDD / 0.4VDD 1 TTL Gate and CL = 10 pF CONDITIONS
AC Test Load and Waveform
DOUT DOUT
10 pF
25
10 pF
25
V DD
Input
0.6V DD 0.4VDD 0.2V DD Test Point
Output
0.4V DD
Test Point
Test when output from low to high
Test when output from high to low
Read/Write Cycle Timing Parameters
(VDD = 3.3V 5%, VGND = 0V, TA = 0 to 70 C)
PARAMETER Clock Cycle Time Input Set Up Time Input Hold Time Clock to Data Valid
SYM. MIN. TCYC TSU THD TKQ 30 7 0 -
W49V002A MAX. 11
UNIT nS nS nS nS
Reset Timing Parameters
PARAMETER Vdd stable to Reset Active Clock Stable to Reset Active Reset Pulse Width Reset Active to Output Float Reset Inactive to Input Active SYMBOL TPRST TKRST TRSTP TRSTF TRST MIN. 1 100 100 1 TYP. MAX. 50 UNIT mS S nS nS S
Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is input high and (b) low level signal's reference level is input low. Ref. to the AC testing condition.
- 21 -
Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
TIMING WAVEFORMS FOR LPC INTERFACE MODE
Read Cycle Timing Diagram
TCYC
CLK
#RESET
TSU THD
#LFRAM
Memory Read Cycle
TSU THD Start Address A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 1111b TAR
TKQ Sync Data D[3:0] D[7:4] TAR Next Start
0000b
LAD[3:0]
0000b
010Xb
Tri-State 0000b 1 Clock
1 Clock 1 Clock
Load Address in 8 Clocks, the address should be within the top 4MByte, FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
2 Clocks
Data out 2 Clocks
1 Clock
Write Cycle Timing Diagram
TCYC
CLK
#RESET
#LFRAM Memory Write Cycle 011Xb A[31:28] A[27:24]
TSU THD Start Address A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] D[3:0] Data D[7:4] 1111b TAR Tri-State Sync 0000b 1 Clock TAR Next Start 0000b 1 Clock
LAD[3:0]
0000b
1 Clock 1 Clock
Load Data in 2 Clocks Load Address in 8 Clocks, the address should be within the top 4MByte, FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
2 Clocks
- 22 -
Preliminary W49V002A
Program Cycle Timing Diagram
CLK
#RESET
#LFRAM
Memory Write
1st Start Cycle LAD[3:0]
0000b
Address
A[31:28] A[27:24] A[23:20] A[19:16] X101b 0101b 0101b 0101b
Data
1010b 1010b
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR
Start next command
011Xb
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
Write the 1st command to the device in LPC mode.
CLK #RESET
#LFRAM
2nd Start Cycle LAD[3:0]
0000b
Memory Write
Address
A[31:28] A[27:24] A[23:20] A[19:16] X010b 1010b 1010b 1010b
Data
0101b 0101b
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR
Start next command
011Xb
1 Clock
1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
Memory Write A[31:28] A[27:24] A[23:20]
3rd Start Cycle LAD[3:0]
0000b
Address
A[19:16] X101b 0101b 0101b 0101b
Data
0000b 1010b
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR
Start next command
011Xb
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "A0" in 2 Clocks
2 Clocks
1 Clock
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM
Memory Write Cycle 011Xb A[31:28] A[27:24] A[23:20]
Internal program start 4th Start Address
A[19:16] A[15:12] A[11:8] A[7:4] A[3:0]
Data
D[3:0] D[7:4]
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR Internal program start
LAD[3:0]
0000b
1 Clock 1 Clock
Load Ain in 8 Clocks
Load Din in 2 Clocks
2 Clocks
Write the 4th command(target location to be programmed) to the device in LPC mode. All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
- 23 -
Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
Timing Waveforms for LPC Interface Mode, continued
#DATA Polling Timing Diagram
CLK
#RESET
#LFRAM Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb
An[31:28] An[27:24]
Address
An[23:20] An[19:16] An[15:12] An[11:8] An[7:4] An[3:0]
Data Dn[3:0] Dn[7:4] 1111b
TAR Tri-State
Sync 0000b TAR
Start next command 0000b
1 Clock 1 Clock
Load Address "An" in 8 Clocks
Load Data "Dn" in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the last command(program or erase) to the device in LPC mode.
CLK #RESET XXXXb #LFRAM Memory Read Cycle 010Xb
An[31:28] An[27:24] An[23:20]
Start LAD[3:0] 0000b
Address
An[19:16] An[15:12] An[11:8] An[7:4] An[3:0]
TAR 1111b Tri-State
Sync 0000b
Data XXXXb Dn7,xxx TAR
Next Start 0000b
1 Clock 1 Clock
Load Address in 8 Clocks
2 Clocks
1 Clock Data out 2 Clocks
1 Clock
Read the DQ7 to see if the internal write complete or not.
CLK
#RESET
#LFRAM Start LAD[3:0] 0000b Memory Read Cycle 010Xb
An[31:28] An[27:24] An[23:20]
Address
An[19:16] An[15:12] An[11:8] An[7:4] An[3:0]
TAR 1111b
Sync
Data XXXXb Dn7,xxx TAR
Next Start 0000b
Tri-State 0000b
1 Clock 1 Clock
Load Address in 8 Clocks
2 Clocks
1 Clock Data out 2 Clocks
1 Clock
When internal write complete, the DQ7 will equal to Dn7. All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
- 24 -
Preliminary W49V002A
Timing Waveforms for LPC Interface Mode, continued
Toggle Bit Timing Diagram
CLK
#RESET
#LFRAM Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb
A[31:28] A[27:24] A[23:20]
Address
A[19:16] A[15:12] A[11:8] A[7:4] A[3:0]
Data D[3:0] D[7:4] 1111b
TAR Tri-State
Sync 0000b TAR
Start next command
1 Clock 1 Clock
Load Address "An" in 8 Clocks
Load Data "Dn" in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the last command(program or erase) to the device in LPC mode.
CLK #RESET
#LFRAM Memory Read Cycle 010Xb
A[31:28] A[27:24] A[23:20]
Start LAD[3:0] 0000b
Address
A[19:16]
TAR XXXXb XXXXb XXXXb XXXXb 1111b Tri-State
Sync 0000b
Data XXXXb
X,D6,XXb
Next Start TAR 0000b
1 Clock 1 Clock
Load Address in 8 Clocks
2 Clocks
1 Clock Data out 2 Clocks
1 Clock
Read the DQ6 to see if the internal write complete or not.
CLK
#RESET
#LFRAM Start LAD[3:0] 0000b Memory Read Cycle 010Xb
A[31:28] A[27:24] A[23:20]
Address
A[19:16]
TAR XXXXb XXXXb XXXXb XXXXb 1111b Tri-State
Sync 0000b
Data XXXXb
X,D6,XXb
Next Start TAR 0000b
1 Clock 1 Clock
Load Address in 8 Clocks
2 Clocks
1 Clock Data out 2 Clocks
1 Clock
When internal write complete, the DQ6 will stop toggle. All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
- 25 -
Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
Timing Waveforms for LPC Interface Mode, continued
Boot Block Lockout Enable Timing Diagram
CLK
#RESET
#LFRAM Memory Write 1st Start Cycle LAD[3:0] Address X101b 0101b 0101b 0101b Data 1010b 1010b TAR 1111b Tri-State Sync 0000b TAR Start next command
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16]
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks Write the 1st command to the device in LPC mode.
2 Clocks
1 Clock
1 Clock
CLK #RESET
#LFRAM Memory Write 2nd Start Cycle LAD[3:0] Start next command TAR
Address X010b 1010b 1010b 1010b
Data 0101b 0101b
TAR 1111b Tri-State
Sync 0000b
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16]
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks Write the 2nd command to the device in LPC mode.
2 Clocks
1 Clocks
1 Clock
CLK #RESET
#LFRAM Memory Write 3rd Start Cycle LAD[3:0] 0000b 011Xb Start next command TAR
Address A[31:28] A[27:24] A[23:20] A[19:16] X101b 0101b 0101b
Data 0101b 0000b 1000b
TAR 1111b Tri-State
Sync 0000b
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "80" in 2 Clocks Write the 3rd command to the device in LPC mode.
2 Clocks
1 Clock
1 Clock
CLK
#RESET
#LFRAM Memory Write 4th Start Cycle 0000b 011Xb
Address A[31:28] A[27:24] A[23:20] A[19:16] X101b 0101b 0101b 0101b
Data 1010b 1010b
TAR 1111b Tri-State
LAD[3:0]
Sync 0000b TAR
Start next command
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks Write the 4th command to the device in LPC mode.
2 Clocks
1 Clock
1 Clock
CLK #RESET
#LFRAM Memory Write 5th Start Cycle LAD[3:0] 0000b 011Xb
Address A[31:28] A[27:24] A[23:20] A[19:16] X010b 1010b 1010b 1010b
Data 0101b 0101b
TAR 1111b Tri-State
Sync 0000b TAR
Start next command
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks Write the 5th command to the device in LPC mode.
2 Clocks
1 Clock
1 Clock
CLK
#RESET
#LFRAM Memory Write 6th Start Cycle LAD[3:0] 0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] X101b 0101 b 0101b
Internal program start Address Data 0101b 0000b 0100b TAR 1111b Tri-State Sync 0000b TAR Internal program start
1 Clock 1 Clock
Load Address "5555" 8 Clocks Write the 6th command to the device in LPC
Load Data "40" in 2 Clocks mode.
2 Clocks
1 Clock
All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
- 26 -
Preliminary W49V002A
Timing Waveforms for LPC Interface Mode, continued
Chip Erase Timing Diagram
CLK
#RESET
#LFRAM Memory Write Cycle 011Xb A[31:28] A[27:24] A[23:20] Start next command TAR
1st Start LAD[3:0] 0000b
Address A[19:16] X101b 0101b 0101b 0101b
Data 1010b 1010b 1111b
TAR Tri-State
Sync 0000b
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
CLK #RESET
#LFRAM Memory Write Cycle 011Xb A[31:28] A[27:24] A[23:20]
2nd Start LAD[3:0] 0000b
Address A[19:16] X010b 1010b 1010b 1010b
Data 0101b 0101b 1111b
TAR Tri-State
Sync 0000b TAR
Start next command
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the 2nd command to the device in LPC mode.
CLK #RESET
#LFRAM Memory Write Cycle 011Xb A[31:28] A[27:24] A[23:20]
3rd Start LAD[3:0] 0000b
Address A[19:16] X101b 0101b 0101b 0101b 0000b
Data 1000b 1111b
TAR Tri-State
Sync 0000b TAR
Start next command
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "80" in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM Memory Write Cycle 011Xb A[31:28] A[27:24] A[23:20]
LAD[3:0]
4th Start 0000b
Address A[19:16] X101b 0101b 0101b 0101b
Data 1010b 1010b 1111b
TAR Tri-State
Sync 0000b TAR
Start next command
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the 4th command to the device in LPC mode.
CLK
#RESET
#LFRAM Memory Write Cycle 011Xb A[31:28] A[27:24] A[23:20]
5th Start LAD[3:0] 0000b
Address A[19:16] X010b 1010b 1010b 1010b
Data 0101b 0101b 1111b
TAR Tri-State
Sync 0000b TAR
Start next command
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the 5th command to the device in LPC mode.
CLK
#RESET
#LFRAM Internal erase start Memory Write Cycle 011Xb A[31:28] A[27:24] A[23:20] Address A[19:16] X101b 0101b 0101b 0101b 0000b Data 0001b 1111b TAR Tri-State Sync 0000b TAR Internal erase start
6th Start LAD[3:0] 0000b
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "10" in 2 Clocks
2 Clocks
1 Clock
Write the 6th command to the device in LPC mode. All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
- 27 -
Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
Timing Waveforms for LPC Interface Mode, continued
Sector Erase Timing Diagram
CLK
#RESET
#LFRAM Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock Address A[31:28] A[27:24] A[23:20] A[19:16] X101b 0101b 0101b 0101b Data 1010b 1010b TAR 1111b Tri-State Sync 0000b 1 Clock TAR 1 Clock Start next command
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
Write the 1st command to the device in LPC mode.
CLK #RESET
#LFRAM Memory Write 2nd Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock
Address A[31:28] A[27:24] A[23:20] A[19:16] X010b 1010b 1010b 1010b
Data 0101b 0101b
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR
Start next command
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
Write the 2nd command to the device in LPC mode.
CLK #RESET
#LFRAM Memory Write 3rd Start Cycle LAD[3:0] 0000b 011Xb 1 Clocks 1 Clocks
Address A[31:28] A[27:24] A[23:20] A[19:16] X101b 0101b 0101b
Data 0101b 0000b 1000b
TAR 1111b Tri-State
Sync 0000b 1 Clocks TAR
Start next command
Load Address "5555" in 8 Clocks
Load Data "80" in 2 Clocks
2 Clocks
1 Clocks
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM Memory Write 4th Start Cycle 0000b 011Xb 1 Clock 1 Clock
LAD[3:0]
Address A[31:28] A[27:24] A[23:20] A[19:16] X101b 0101b 0101b 0101b
Data 1010b 1010b
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR
Start next command
Load Address "5555" in 8 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
Write the 4th command to the device in LPC mode.
CLK #RESET
#LFRAM Memory Write 5th Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock
Address A[31:28] A[27:24] A[23:20] A[19:16] X010b 1010b 1010b 1010b
Data 0101b 0101b
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR
Start next command
Load Address "2AAA" in 8 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
Write the 5th command to the device in LPC mode.
CLK #RESET
#LFRAM Memory Write 6th Start Cycle LAD[3:0]
Internal erase start Address
SA[15:12]
Data XXXXb XXXXb XXXXb 0000b 0011b
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR Internal erase start
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] 1 Clock 1 Clock
Load Sector Address in 8 Clocks
Load Din in 2 Clocks
2 Clocks
Write the 6th command(target sector to be erased) to the device in LPC mode. All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
- 28 -
Preliminary W49V002A
Timing Waveforms for LPC Interface Mode, continued
GPI Register Readout Timing Diagram
CLK #RESET
#LFRAM Memory Read Cycle 010Xb A[31:28] A[27:24]
Start LAD[3:0] 0000b
Address A[23:20] A[19:16] 0000b 0001b 0000b 0000b 1111b
TAR Tri-State
Sync 0000b
Data D[3:0] D[7:4] TAR
Next Start 0000b
1 Clock 1 Clock
Load Address "FFBC0100(hex)" in 8 Clocks
2 Clocks
1 Clock Data out 2 Clocks
1 Clock
Note: Read the DQ[4:0] to capture the states(High or Low) of the GPI[4:0] input pins. The DQ[7:5] are reserved pins.
Reset Timing Diagram
VDD
TPRST
CLK TKRST TRSTP #RESET TRST
F
TRST
LAD[3:0]
#LFRAM
- 29 -
Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
ORDERING INFORMATION
PART NO. ACCESS TIME (nS) W49V002AP W49V002AQ
Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
POWER SUPPLY CURRENT MAX. (mA) 25 25
STANDBY VDD CURRENT MAX. ( A) 20 20
PACKAGE
11 11
32L PLCC 32L STSOP
- 30 -
Preliminary W49V002A
PACKAGE DIMENSIONS
32L PLCC
Symbol
HE E 4 1 32 30
Dimension in Inches
Dimension in mm
Min.
0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075
Nom. Max.
0.140
Min.
0.50
Nom.
Max.
3.56
5
29
GD D HD
13
21
A A1 A2 b1 b c D E e GD GE HD HE L y Notes:
0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090
0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004
2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91
2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29
2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10
0
10
0
10
14
20
c
1. 2. 3. 4.
L A2 A
Dimensions D & E do not include interlead flash. Dimension b1 does not include dambar protrusion/intrusion. Controlling dimension: Inches General appearance spec. should be based on final visual inspection sepc.
Seating Plane
e
b b1 GE
A1
y
32L STSOP(8 x 14mm)
HD D c
Symbol Dimension in Inches Min. Nom. Max.
0.047 0.002 0.035 0.007 0.004 0.040 0.009 ----0.488 0.315 0.551 0.020 0.020 0.024 0.031 0.000 0 3 0.004 5 0.00 0 3 0.028 0.50 0.006 0.041 0.010 0.008 0.05 0.95 0.17 0.10 1.00 0.22 ----12.40 8.00 14.00 0.50 0.60 0.80 0.10 5 0.70
Dimension in mm Min. Nom. Max.
1.20 0.15 1.05 0.27 0.21
e
E A A1 A2 b c D E HD e L L1 Y
b
c L L1 A1 2 A A Y
- 31 -
Publication Release Date: April 2001 Revision A1
Preliminary W49V002A
VERSION HISTORY VERSION A1 DATE Apr. 2001 PAGE Initial Issued DESCRIPTION
Headquarters
Winbond Electronics (H.K.) Ltd.
Unit 9 -15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science -Based Industrial Park, Hsinchu, Taiwan Kowloon, Hong Kong TEL: 852-27513100 TEL: 886 -3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax -on-demand: 886 -2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min -Sheng East Rd., Taipei, Taiwan TEL: 886 -2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change withou t notice.
- 32 -

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